Protection of layout designs (topographies) of integrated circuits : R. I. P.?
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Protection of layout designs (topographies) of integrated circuits : R. I. P.?
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| Physical Description |
648-658 |
|---|---|
| Language |
English |
| Language of Original Work |
English |
| Publisher |
2001.
|
| Series | IIC : International Review of Industrial Property and Copyright Law, ISSN 0018-9855; 32 (6) |
| Subjects | |
| Additional Information | Gunnar Karnell |