Protection of layout designs (topographies) of integrated circuits : R. I. P.?
Finna-recension
Protection of layout designs (topographies) of integrated circuits : R. I. P.?
Sparad:
| Fysisk beskrivning |
648-658 |
|---|---|
| Språk |
engelska |
| Originalverkets språk |
engelska |
| Utgivare |
2001.
|
| Serie | IIC : International Review of Industrial Property and Copyright Law, ISSN 0018-9855; 32 (6) |
| Ämnen | |
| Mer information | Gunnar Karnell |